Hardware implementation of a pipelined turbo decoder

Wang, Guan (2010) Hardware implementation of a pipelined turbo decoder. Masters thesis, Memorial University of Newfoundland.

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Turbo codes have been widely studied since they were first proposed in 1993 by Berrou, Glavieux, and Thitimajshima in "Near Shannon Limit error-correcting coding and decoding: Turbo-codes" [1]. They have the advantage of providing a low bit error rate (BER) in decoding, and outperform linear block and convolutional codes in low signal-to-noise-ratio (SNR) environments. The decoding performance of turbo codes can be very close to the Shannon Limit, about 0.7decibel (dB). It is determined by the architectures of the constituent encoders and interleaver, but is bounded in high SNRs by an error floor. Turbo codes are widely used in communications. We explore the codeword weight spectrum properties that contribute to their excellent performance. Furthermore, the decoding performance is analyzed and compared with the free distance asymptotic performance. A 16-state turbo decoder is implemented using VHSIC Hardware Description Language (VHDL) and then mapped onto a field-programmable gate array (FPGA) board. The hardware implementations are compared with the software simulations to verify the decoding correctness. A pipelined architecture is then implemented which significantly reduces the decoding latency. -- Keywords: turbo codes; decoding performance; Monte Carlo simulations; FPGA implementation

Item Type: Thesis (Masters)
URI: http://research.library.mun.ca/id/eprint/8822
Item ID: 8822
Additional Information: Includes bibliographical references (leaves 91-94).
Department(s): Engineering and Applied Science, Faculty of
Date: 2010
Date Type: Submission
Library of Congress Subject Heading: Decoders (Electronics)--Design and construction; Error-correcting codes (Information theory); Monte Carlo method; VHDL (Computer hardware description language)

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