Fast parasitic-aware synthesis methodology for high performance analog and RF circuits

Ahmed, Abdullah Al Iftekhar (2012) Fast parasitic-aware synthesis methodology for high performance analog and RF circuits. Masters thesis, Memorial University of Newfoundland.

[English] PDF (Migrated (PDF/A Conversion) from original format: (application/pdf)) - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. Download (31MB) [English] PDF - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. (Original Version)

Abstract

In this work, a fast parasitic-aware synthesis approach of CMOS analog and RF circuits is presented. Traditionally in layout-aware synthesis approaches, the optimization of analog and RF circuits is attained by two separate stages. The circuit sizing stage which is mostly implemented by using some evolutionary algorithms along with certain commercial off the shelf simulators is followed by layout generation, extraction and verification. This loop continues until convergence is found. In this thesis, a fast parasitic-aware method, which considers the circuit performance constraints and layout induced parasitic simultaneously within a concurrent phase of circuit synthesis by using convex optimization problem, is proposed. The proposed methodology is used to optimize and verify the performance of five high performance analog circuits and two RF circuits in two different CMOS technologies. The synthesis time is found to be under a few seconds and the experimental results demonstrate the high efficacy of this fast parasitic-aware synthesis approach.

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