Analysis of performance limitations in multithreaded multiprocessor architectures

Zuberek, W. M. (2001) Analysis of performance limitations in multithreaded multiprocessor architectures. In: Second International Conference on Application of Concurrency to System Design, 25-29 June 2001, Newcastle upon Tyne, UK.

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The performance of modern multiprocessor systems is increasingly limited by interconnection delays or long latencies of memory subsystems. Instruction-level multithreading is a technique to tolerate such long latencies by switching from one instruction thread to another and continuing instruction execution concurrently with the long-latency operations. Using timed Petri net models, the paper analyzes performance limitations introduces by different components of distributed-memory multithreaded multiprocessor systems. Simulation results are used to compare performance improvements obtained by replicating critical components of the system to those obtained using components with better performance characteristics.

Item Type: Conference or Workshop Item (Paper)
Item ID: 14619
Department(s): Science, Faculty of > Computer Science
Date: June 2001
Date Type: Completion
Digital Object Identifier (DOI):
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