Modeling and Analysis of Dual Block Multithreading

Zuberek, W. M. (2004) Modeling and Analysis of Dual Block Multithreading. In: FORTE 2004, September 27-30, 2004, Toledo, Spain. (Submitted)

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Instruction level multithreading is a technique for tolerating long– latency operations (e.g., cache misses) by switching the processor to another thread instead of waiting for the completion of a lengthy operation. In block mul- tithreading, context switching occurs for each initiated long–latency operation. However, processor cycles during pipeline stalls as well as during context switch- ing are not used in typical block multithreading, reducing the performance of a processor. Dual block multithreading introduces a second active thread which is used for instruction issuing whenever the original (main) thread becomes in- active. Dual block multithreading can be regarded as a simple and specialized case of simultaneous multithreading when two (simultaneous) threads are used to issue instructions for a single pipeline. The paper develops a simple timed Petri net model of a dual block multithreading and uses this model to estimate the performance improvements of the proposed dual block multithreading.

Item Type: Conference or Workshop Item (Paper)
Item ID: 14563
Keywords: Block multithreading, instruction issuing, pipelined processors, timed Petri nets, performance analysis, event–driven simulation
Department(s): Science, Faculty of > Computer Science
Date: 2004
Date Type: Submission
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