Performance evaluation of network-on-chip architectures

Chen, Jie (2012) Performance evaluation of network-on-chip architectures. Masters thesis, Memorial University of Newfoundland.

[English] PDF (Migrated (PDF/A Conversion) from original format: (application/pdf)) - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. Download (41MB) [English] PDF - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. (Original Version)

Abstract

With the development of integrated circuit technology, System-on-Chip (SoC), which is composed of heterogeneous cores on a single chip, has entered the billion-transistor era. As the microprocessor industry moves from single-core to multi-core, and eventually to many-core architectures, providing tens to hundreds of similar cores on a single multiprocessor chip will be necessary. Efficient communication among different processors becomes critical. Therefore, a high-performance, flexible, scalable, and design-friendly interconnection architecture is highly desired for modern SoC and microprocessor designs. -- How to provide efficient communication within a SoC architecture poses a challenge to both academia and industry. Before the advent of Network-on-Chip (NoC), interconnection architectures were usually based on dedicated wires or shared buses. However, they cannot be easily scaled up to meet the ever-increasing demand from the on-chip systems. NoC has been proposed as a highly structured and scalable solution to address the communication problems in on-chip systems. NoC has several advantages over dedicated wiring and buses, e.g., high bandwidth, low latency, low power consumption, and scalability. For NoCs, messages are transported back and forth via the interconnection networks. Thus, the interconnections among multiple cores on a chip have a significant impact on communication efficiency and the performance of a chip design in terms of end-to-end delay, throughput, and packets loss ratio. Therefore, it is worthwhile studying the different characteristics of different interconnection network topologies. Another vital factor which can affect network performance is the particular communications requirements of the applications. Without targeting any specific applications, spatial and temporal distributions are explored to study the performance of various interconnection network architectures. It is clearly reflected through our study that networks of different architectures can perform differently under various traffic conditions. In this thesis, the most popular topologies and some recent topologies are reviewed and compared, and Three target architectures are chosen: torus (a representative topology of recent topologies), Metacube (a representative topology of recent topologies) and hypercube (a representative topology of popular topologies with relatively high cost). Their performance under different traffic models is studied. Three temporal distributions including Poisson, MMPP and Pareto, and three spatial distributions including bit-complement, random uniform and hot spot, are discussed in this thesis. Based on the simulation results, strengths and limitations of the torus, the Metacube and the hypercube are summarized.

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