Layout-aware sizing methodology for analog integrated circuits

Liao, Tuotian (2021) Layout-aware sizing methodology for analog integrated circuits. Doctoral (PhD) thesis, Memorial University of Newfoundland.

[English] PDF - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. Download (4MB)

Abstract

The traditional iterative design flows for analog integrated circuit synthesis, which can help meet circuit performance requirements in the conventional technology processes, often experience longer runtime. The nonnegligible impact of layout parasitics and layout dependent effects (LDEs) on electrical performance has posed increasingly greater challenges to determining circuit parameters (i.e., circuit sizing), which makes it harder for designers to close the synthesis loop especially in the advanced nanometer technologies. This dissertation is focused on parasitic-aware and LDE-aware circuit sizing solutions in the early schematic design stage of the circuit synthesis process. A number of techniques, which include analytical modeling for devices and circuits, mathematical programming, sensitivity analysis, curve fitting, and heuristic optimization as well as machine learning, are utilized to construct the proposed circuit sizing methodologies. In this regard, we combine geometric programming and differential evolution as well as a many-objective evolutionary algorithm to construct a novel two-phase hybrid sizing methodology for dealing with parasitics. In addition, we propose to use gm/ID-based mixed-integer nonlinear programming to improve the accuracy of the first-phase sizing, and adapt it to address the layout-dependent effects with the aid of sensitivity analysis. Furthermore, we develop a machine-learning based approach called Bayesian optimization featuring high-dimensionality and many objectives to tackle parasitics and LDEs for analog circuit sizing. The ultimate objective of this research is to develop efficient methodologies and algorithms to include the consideration of parasitics and LDEs from layout design into schematic design stage as an early action to reduce the analog IC design iterations. The experimental results show the efficacy of our proposed sizing methodologies over other similar works for the layout-aware analog circuit sizing.

Actions (login required)

View Item