Performance bounds for distributed memory multithreaded architectures

Zuberek, W. M. (1998) Performance bounds for distributed memory multithreaded architectures. In: 1998 IEEE International Conference on Systems, Man, and Cybernetics, 14 Oct. 1998, San Diego, CA, USA.

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In distributed memory multithreaded systems, the long memory latencies and unpredictable synchronization delays are tolerated by context switching, i.e., by suspending the current thread and switching the processor to another thread waiting for execution. Simple analytical upper bounds on performance measures are derived using throughput analysis and extreme values of some model parameters. These derived bounds are compared with performance results obtained by simulation of a detailed model of the analyzed architecture.

Item Type: Conference or Workshop Item (Paper)
Item ID: 14793
Department(s): Science, Faculty of > Computer Science
Date: 14 October 1998
Date Type: Completion
Digital Object Identifier (DOI):
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