Performance limitations of block-multithreaded distributed-memory systems

Zuberek, W. M. (2009) Performance limitations of block-multithreaded distributed-memory systems. In: 2009 Winter Simulation Conference (WSC), 13-16 December, 2009, Austin, TX, USA.

[img] [English] PDF (The version available in this research repository is a postprint. It has the same peer-reviewed content as the published version, but lacks publisher layout and branding.) - Accepted Version
Available under License Creative Commons Attribution Non-commercial.

Download (139kB)


The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results

Item Type: Conference or Workshop Item (Paper)
Item ID: 14585
Department(s): Science, Faculty of > Computer Science
Date: December 2009
Date Type: Completion
Digital Object Identifier (DOI):
Related URLs:

Actions (login required)

View Item View Item


Downloads per month over the past year

View more statistics