Zuberek, W. M. (2009) Performance limitations of block-multithreaded distributed-memory systems. In: 2009 Winter Simulation Conference (WSC), 13-16 December, 2009, Austin, TX, USA.
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Abstract
The performance of modern computer systems is increasingly often limited by long latencies of accesses to the memory subsystems. Instruction-level multithreading is an architectural approach to tolerating such long latencies by switching instruction threads rather than waiting for the completion of memory operations. The paper studies performance limitations in distributed-memory block multithreaded systems and determines conditions for such systems to be balanced. Event-driven simulation of a timed Petri net model of a simple distributed-memory system confirms the derived performance results
| Item Type: | Conference or Workshop Item (Paper) |
|---|---|
| URI: | http://research.library.mun.ca/id/eprint/14585 |
| Item ID: | 14585 |
| Department(s): | Science, Faculty of > Computer Science |
| Date: | December 2009 |
| Date Type: | Completion |
| Digital Object Identifier (DOI): | http://dx.doi.org/10.1109/WSC.2009.5429718 |
| Related URLs: |
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