Design, simulation and implementation of enhanced crossbar combined input-output queued switch architecture

Awan, Atiq (2004) Design, simulation and implementation of enhanced crossbar combined input-output queued switch architecture. Masters thesis, Memorial University of Newfoundland.

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Abstract

The rapid growth in communication networks has led to an exponential increase in the traffic volumes thus requiring high-speed switches and routers, with high bandwidth, at the nodes. The networking research community has focused its effort on the development of high-bandwidth switches. However, advances in data transmission technology, particularly the development and use of the optical technology, have enabled reliable high transmission bandwidth at a relatively low cost. On the other hand, neither switches nor routers have kept pace with this development. Therefore, the switches and routers are increasingly becoming performance bottlenecks in high-bandwidth communication. -- Until recently, most of the packet switches were based on output queueing due to its ability to provide high throughput. However due to the slow memory speeds compared to link bandwidth, output queued switches are no longer feasible for high-speed switching. In this work, we consider building a combined input-output queued packet-switch using multiple crossbars, which forms a step forward towards obtaining a better solution for high performance packet switching. In particular, we consider multiplane switch architecture with four crossbars in parallel. These crossbars transfer up to four packets to each output line to provide the high throughput however operating at the same speed as the line rate. -- We investigate the performance of this architecture under both uniform and non-uniform traffic arrival patterns and show through simulation that this architecture approximately emulates the pure output queued switch. This architecture employs pipelined scheduling, which eliminates the traffic scheduling overhead and provides a large time window for implementing fair but complex scheduling algorithms. -- Finally, we describe the implementation of this architecture in VLSI using 0.18-micron CMOS standard cell technology. The distributed control leads to a high-speed implementation. We report on the design complexity and discuss implementation results.

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