Compact hardware implementation of advanced encryption standard with concurrent error detection

Yu, Namin (2005) Compact hardware implementation of advanced encryption standard with concurrent error detection. Masters thesis, Memorial University of Newfoundland.

[English] PDF - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. Download (6MB)

Abstract

A compact, efficient and highly reliable implementation of the Advanced Encryption Standard (AES) is the desirable encryption core for any practical low-end embedded application. In this thesis we design and implement a compact hardware AES system with concurrent error detection. -- We investigate various architectures for compact AES implementations in 0.18 μm CMOS technology. We first explore a new compact digital hardware implementation of the AES s-boxes applying the discovery of linear redundancy in the AES s-boxes. Although the new circuit has a small size, the speed of this implementation is also reduced. Encryption architectures without key scheduling that employ four s-boxes and only one s-box are implemented using the new AES s-boxes, as well as based on other compact s-box structures. The comparison of the implementations based on different architectures and s-box structures indicates that the implementation using four s-boxes based on arithmetic operations in GF(2⁴) has the best trade-off of area and speed. Therefore, using this s-box implementation, a complete encryption-decryption architecture with key scheduling employing the four s-box structure is implemented. In order to be adaptive to various practical applications, we optimize the implementation with the four s-box structure to support five different operation modes. -- In addition, high reliability and resistance to malicious attacks are achieved by applying concurrent error detection technology. After the studies of fault models and practical fault induction techniques, two concurrent error detection schemes based on both parity code and hardware redundancy are proposed and implemented. The proposed 16-bit and 32-bit parity code based concurrent error detection schemes achieve 100% detection for single injected faults and detection of many multiple faults with about 67% hardware overhead to the original AES compact hardware implementation.

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