Singh, Karunesh Pratap (1992) On-line reconfiguration of systolic arrays. Masters thesis, Memorial University of Newfoundland.
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Various existing reconfiguration algorithms for array processors cannot be used efficiently for on-line reconfiguration of the array because they require a central processor to initiate and control the reconfiguration. In addition, most of the existing algorithms assume that the switching network is operationally fault-free. -- This report presents an on-line reconfiguration scheme for array processors. The proposed algorithm can tolerate both processing element failure and switching network failure. The processing elements and switches are of a self-testing type and link failures are detected by the processing elements (by using parity bit checks). -- The array is provided with a bottom row of spare cells and when a processing element detects either a self fault or a link failure, it invokes the reconfiguration. A downward global shift (for the particular column) is performed to accomplish the reconfiguration. A number of reconfiguration requests are generated by the processing elements and switch modules to facilitate the reconfiguration. The network is modified and links for propagation of reconfiguration request are added. This scheme makes full use of non-faulty partial results and it blocks the faulty partial results. -- The reconfiguration in the case of a processing element failure is completed in two stages while the reconfiguration in the case of a link failure is completed in a single stage. The links are duplicated to achieve redundancy and in the case of a link failure the spare link is used.
|Item Type:||Thesis (Masters)|
|Additional Information:||Bibliography: leaves 123-125.|
|Department(s):||Engineering and Applied Science, Faculty of|
|Library of Congress Subject Heading:||Systolic array circuits; Array processors|
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