Jiang, Zhi-Jian (1992) A study of two-rail totally self-checking circuits. Masters thesis, Memorial University of Newfoundland.
PDF (Migrated (PDF/A Conversion) from original format: (application/pdf))
- Accepted Version
Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission.
In order to overcome the limitations of conventional design techniques of totally self-checking (TSC) circuits and provide simple, convenient, and systematic design techniques, we formalize a new two-element morphic Boolean algebra — strong morphic Boolean algebra Bsm — and propose a new classification of checkers. Based on these, we have developed three types of universal two-rail (TR) totally self-checking (TSC) basic building blocks (BBB) — EIS BBBs, EISS BBBs, and EIIS BBBs. Besides, a group of TR-TSC multi-function BBBs has also been proposed. These BBBs, like ordinary logic gates in common digital circuits, can be easily used to implement any arbitrary combinational logic using our proposed design rules. The resulting circuit is a TR-TSC circuit. -- A simple interconnection method (SIM) and an image design method (IDM) for the design of TR-TSC circuits have been proposed. The SIM is suitable for the case that the self-testing property can be easily achieved or verified. The IDM deals with the general case that includes complicated logic functions with a large number of inputs. -- We also present a new method to design a TSC circuit with separate error-input indication (EI) and separate internal fault indication (IF). This objective has been achieved by using a new BBB — a TR-TSC decoupling BBB (DC₂). -- An efficient method of diagnosing relevant error sources has been studied. With the help of decoupling circuits consisting of DC₂'s, the error status of relevant inputs and outputs can be indicated. This greatly improves localizability and enhances maintainability. A totally new circuit concept named error-confining circuit has been introduced. TR-TSC error-confining (ECF) circuits implement given logic functions during fault-free operation. But when any internal fault from a prescribed set of faults occurs, the circuit automatically forms several independent areas which are surrounded by isolation boundaries. Thus, the fault is confined to a special area and indicated. This property enhances localizability, maintainability and availability. A TSC double-input decoupling (DIDC) BBB, which is a key component to be used in constructing the isolation boundaries, has been developed. -- The design problems of TSC sequential BBBs have also been discussed. A scheme for designing TSC D flip-flop has been proposed. -- In addition, we have also developed an efficient combinational TSC checker for l-out-of-3 code. The proposed checker uses less hardware, has fewer gate levels, and possesses a higher test capability.
|Item Type:||Thesis (Masters)|
|Additional Information:||Bibliography: leaves 139-148.|
|Department(s):||Engineering and Applied Science, Faculty of|
|Library of Congress Subject Heading:||Digital electronics; Logic circuits--Design; Algebra, Boolean|
Actions (login required)