VLSI implementation of a turbo encoder/decoder

Padinjare, Sainath (2003) VLSI implementation of a turbo encoder/decoder. Masters thesis, Memorial University of Newfoundland.

[English] PDF (Migrated (PDF/A Conversion) from original format: (application/pdf)) - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. Download (5MB) [English] PDF - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. (Original Version)

Abstract

This thesis describes a hardware implementation of a Turbo encoder/decoder. -- Turbo codes, introduced in 1993, enable reliable communications over power- constrained communications channels close to the Shannon limit. Since turbo codecs are employed in battery-powered devices such as cellular phones and laptop computers, power dissipation, along with speed and area, are major concerns in very large scale integrated circuit (VLSI) design. -- There is thus the need for low power, modular, and parallel application-specific integrated circuits (ASICs) for turbo code encoders/decoders using VLSI techniques. -- Possible algorithms for turbo decoding are the soft-output Viterbi algorithm (SOVA) and the Bahl, Cocke, Jelink, and Raviv (BCJR) Algorithm. In this research, the hardware implementation of a low-power turbo encoder and SOVA based decoder for wireless communications applications is investigated. -- SOVA, which is a modification of the Viterbi algorithm(VA) has lower computational and implementation complexity. The turbo decoding process is sequential in nature, so very high speed implementations are difficult to obtain. -- By means of software simulation, the basic turbo encoding/decoding performance is first studied, then the effect of fixed-point arithmetic on the performance of the decoder is analyzed. -- The power dissipation depends mainly on the switching of signal values in the path management unit of the decoder and on the number of iterations of decoding. Certain known power reduction techniques are implemented. -- The performance of the implemented decoder is analyzed and finally conclusions and recommendations for future work are presented. The implementation has been carried out using custom ASIC 0.18 µm CMOS technology.

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