Modeling, analysis and design of the input controller for ATM switches

Wu, Dongmei (2001) Modeling, analysis and design of the input controller for ATM switches. Masters thesis, Memorial University of Newfoundland.

[English] PDF (Migrated (PDF/A Conversion) from original format: (application/pdf)) - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. Download (13MB) [English] PDF - Accepted Version Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission. (Original Version)

Abstract

In broadband communication networks, commonly used traffic rates are of the order of gigabits per second, or even terabits per second. The nodes of the networks, also known as switches or routers, are among the primary technology barriers that hinder the deployment of fast speed networks, while the modern optical fibre technology allows the transmission media to meet the application requirements. Within the switch itself, routing table lookup is the worst bottleneck. Among the proposed Multistage Interconnection Network (MIN) architectures for ATM (Asynchronous Transfer Mode) switch fabric, the Balanced Gamma (BG) network has been shown to be reliable, fault-tolerant, efficient, scalable and superior in performance when compared with other MINs with similar hardware complexity. In this thesis, we provide the modeling, analysis and design of the input controller (IC) for ATM switches using BG networks. -- The IC temporarily stores the incoming cells in input buffers, performs routing table lookup, and forwards them to the switch fabric that delivers cells to outgoing lines. A cache-based IC architecture improves the efficiency by locally storing the frequently used forwarding information. We realize this purpose by high-speed cache attempts followed by slower routing table lookups, if necessary. -- We have developed a simulator to evaluate different schemes to construct the IC. The simulator has the capability of generating traffic following uniform random traffic (URT) and bursty traffic models. Simulation results show that the IC system works well and the system performance can be improved as cache hits occur most of the time. -- Encouraged by the good performance shown, we have developed the hardware implementation for the proposed IC system using Very High Speed Hardware Description Language (VHDL). This is simulated and synthesized using design tools supplied by Model Technology and Synopsys.

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