Heshmatpour, Zahra (2022) Deterministic multi-objective variation-aware analog circuit sizing for carbon nanotube technology. Masters thesis, Memorial University of Newfoundland.
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Abstract
The modern CMOS technology, which is based on Moore’s law semiconductor devices, continuously scales down to achieve higher speed and larger packing density. The need for downscaling of MOSFETs below 45nm technology node results in transistor malfunction due to short channel effects, mobility degradation and higher power consumption. Carbon nanotube field-effect transistors (CNFETs) are one of the promising candidates to substitute CMOS technology for next-generation integrated circuits thanks to their small size and excellent electrical properties, such as quasi-ballistic transport and high carrier mobility. Process variation, such as CNT (Carbon nanotube) diameter, presence of metallic CNTs, misaligned CNTs, high metal-CNT contact resistance and CNT density variations, hinders wide adoption of CNFET technology. As a result, many techniques have been developed to overcome the fabrication variation for digital CNFET circuits while analog CNFET circuits generally lack a proper approach to avoid performance failure. This thesis starts with description of CNT parameters and then considers the most critical parameters that have the greatest impact on analog circuit performance. Then we use a design centering approach for circuit sizing to obtain the optimal value of design parameters against carbon nanotube process variation to ensure to meet the performance specification and enhance the functional robustness. Subsequently, we present a modified method to solve the generalized boundary curve (GBC) optimization as a starting point to develop our fully deterministic multi-objective sizing flow. In the next step we take advantage of the normal boundary intersection (NBI) method in combination with our modified GBC method to develop our multi-objective optimization analog CNFET sizing design methodology considering carbon nanotube parameter process variation. The performance of our methodology is analysed by optimizing two operational amplifier (op-amp) circuits and two current conveyor (CCII) circuits, which are considered to be the common building blocks in the interface circuits to the analog world. The experimental results demonstrate that our proposed method can reach a better approximation to the Pareto front compared to the other state-of-the-art multi-objective methods.
| Item Type: | Thesis (Masters) |
|---|---|
| URI: | http://research.library.mun.ca/id/eprint/15745 |
| Item ID: | 15745 |
| Additional Information: | Includes bibliographical references (pages 82-88) -- Restricted until May 31, 2025 |
| Keywords: | multi-objective optimization, CNFET |
| Department(s): | Engineering and Applied Science, Faculty of |
| Date: | May 2022 |
| Date Type: | Submission |
| Digital Object Identifier (DOI): | https://doi.org/10.48336/65A6-6D64 |
| Library of Congress Subject Heading: | Analog CMOS integrated circuits; Carbon nanotubes |
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