Liao, Haohao (2015) Design of an integrated hardware platform for four different lightweight block ciphers. Masters thesis, Memorial University of Newfoundland.
- Accepted Version
Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission.
In recent years, there are more and more embedded devices with limited hardware resources, such as RFID tags and smart cards. In these devices, since the resources are limited, we need some specially designed cryptographic ciphers to ensure the required security level. Many lightweight block ciphers, such as PRESENT, PRINTcipher, LED and Piccolo, were designed to meet these requirements. In these resource-constrained environments, we need specific hardware implementations for these ciphers to minimize resources. In this thesis, we investigate the hardware implementation of four different, but similar, lightweight block ciphers: PRESENT, Piccolo, PRINTcipher and LED. The purpose of this thesis is to present a common platform which integrates these four ciphers into one system using a shared datapath, with the objective of reducing the area below the total sum of area consumed by the individual ciphers. First, we implement these four ciphers separately, and design a platform which integrates these four ciphers together into a basic iterative design. Then, we compare the resource consumption results of the platform and the four individual ciphers. In addition to the normal iterative design, we also present a serialized design of the platform, which is more compact than the iterative design. The structure and implementation of the platform is clearly stated in the thesis with the target technology being the Altera Cyclone IV FPGA. The final synthesis result shows the whole design has successfully achieved the desired objective of flexibility, low resource consumption and compatibility to many applications. We save a lot of hardware resources by significantly reducing the number of dedicated logic registers and combinational functions used in the FPGA.
|Item Type:||Thesis (Masters)|
|Additional Information:||Includes bibliographical references (pages 101-103).|
|Department(s):||Engineering and Applied Science, Faculty of|
|Library of Congress Subject Heading:||Data encryption (Computer science); Ciphers; Computer security; Embedded computer systems--Design and construction|
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