Zhang, Dianyong (2007) Intermediate representations for parallel languages on CGRAs. Masters thesis, Memorial University of Newfoundland.
- Accepted Version
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Coarse Grained Reconfigurable Arrays (CGRAs) are reconfigurable computing architectures based on word-width processing elements, in contrast to Field Programmable Gate Arrays (FPGAs), which use bit-width processing elements. CGRAs have faster time-to-market than Application Specific Integrated Circuits (ASICs) and, for many applications, faster execution than FPGA. In contrast to traditional sequential language, we aim to develop a parallel object-oriented programming language (HARPO/L), that can be compiled to CGRAs configuration files to execute. This requires that compiler exploits the parallelism from language itself and target architecture. This thesis mainly shows a set of intermediate representations (IR) in the compiler for HARPO/L, which contains all information from the source program and is easier to be analyzed and optimized. -- Based on the HARPO/L language features, we use object dependence graphs (ODGs) to represent the relations among objects. The augmented concurrent control flow graphs show threads among objects. After the interobject analysis and optimizations, an executable dataflow graph, the final IR form, can be produced. The IR can then be used as input to the compiler back end. -- This research offers a significant advance on the HARPO/L Compilation approach. It will benefit to finish advanced HARPO/L programming Language executing in high diversity CGRA architectures.
|Item Type:||Thesis (Masters)|
|Additional Information:||Includes bibliographical references (leaves 112-116).|
|Department(s):||Engineering and Applied Science, Faculty of|
|Library of Congress Subject Heading:||Compilers (Computer programs); Integrated circuits; Object-oriented programming languages|
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