Implementation of selected cryptographic algorithms on a reconfigurable microprocessor platform

Cook, Andrew L. (2003) Implementation of selected cryptographic algorithms on a reconfigurable microprocessor platform. Masters thesis, Memorial University of Newfoundland.

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    Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission.
    (Original Version)

Abstract

This research was performed to evaluate the cryptographic capabilities of the Chameleon CS2112 Reconfigurable Communications Processor. The CS2112 is a processor architecture which closely couples a general purpose microprocessor with a specialized reconfigurable core. -- To evaluate the architecture, five cryptographic algorithms were chosen for implementation. The first algorithm, the Data Encryption Standard (DES), was the United States National Cryptographic Standard from 1977 until 2001 and has been the most widely used cryptographic algorithm in computing and communications environments. DES's successor, the Advanced Encryption Standard (AES or Rijndael) which was chosen in the fall of 2000, was also implemented. Since the CS2112 is targeted toward wireless communications applications the other three algorithms - E0, KASUMI, RC4 - were chosen as they are currently used to provide security in common wireless protocols. The Bluetooth protocol, developed to provide a cheap and easy method for users to create wireless connections between devices, uses E0 to secure connections. The RC4 algorithm is part of the 802.11b wireless data communications standard and KASUMI forms an integral part of the authentication and privacy portions of the 3rd Generation GSM cell phone standard. -- DES and AES were fully implemented on the CS2112 and a working executable application was developed. Our efforts to exploit the parallelism and pipelining capability of the CS2112 and multiple implementations are described for these two algorithms. The maximum throughputs for the DES and AES implementations were found to be 322.5 Mbits/sec and 1.1 Gbits/sec respectively. Also, although complete implementations were not finalized, preliminary implementations for E0, KASUMI, and RC4 were developed with a view to allow performance estimates to be made and provide a basis for future work. -- The Chameleon CS2112 implementations of the above algorithms performed respectably and the architecture could be useful in cryptographic applications. However, the architecture does constrain design size considerably. Unfortunately, the CS2112 is no longer commercially available since Chameleon Systems Inc. has ceased operations. However, this architecture, with some modifications, could be used as the basis for a new general cryptographic accelerator.

Item Type: Thesis (Masters)
URI: http://research.library.mun.ca/id/eprint/7005
Item ID: 7005
Additional Information: Bibliography: leaves 99-106.
Department(s): Engineering and Applied Science, Faculty of
Date: 2003
Date Type: Submission
Library of Congress Subject Heading: Microprocessors; Adaptive computing systems; Data encryption (Computer science); Computer algorithms

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