Design and analysis of auto scaling pulsed analog neural circuits

Bhattacharya, Dipankar (1991) Design and analysis of auto scaling pulsed analog neural circuits. Masters thesis, Memorial University of Newfoundland.

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    Available under License - The author retains copyright ownership and moral rights in this thesis. Neither the thesis nor substantial extracts from it may be printed or otherwise reproduced without the author's permission.
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Abstract

Minimization of synaptic area is important in a neural network with a high synapse to neuron ratio. Consequently one has to optimize the synapse rather than the neuron. A pulsed analog network with amplitude modulation results in a very compact and efficient synapse. Charge summation is used which leads to a single bus as the summer. Membrane capacitance has been distributed to the synapses allowing the network to be perfectly scaled. Like the biological neuron, the neuron fires a single output pulse when the activation exceeds the threshold. A discharge pulse is generated to discharge the membrane capacitances via discharge transistors which have also been distributed to synapses for scaling purposes. Circuit design and detailed analysis has been included along with simulation results. Standard cells have also been presented. As the proposed architecture behaves quite differently from existing architectures, simulation of some of the standard examples of neural networks have been included. Two chips have also been designed using 3μm design rules.

Item Type: Thesis (Masters)
URI: http://research.library.mun.ca/id/eprint/5333
Item ID: 5333
Additional Information: Bibliography: leaves 115-120.
Department(s): Engineering and Applied Science, Faculty of
Date: 1991
Date Type: Submission
Library of Congress Subject Heading: Neural circuitry--Design; Neural networks; Pulse circuits

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