Rhinelander, Jason P. (2003) Design and implementation of encryption algorithms in a coarse grain reconfigurable environment. Masters thesis, Memorial University of Newfoundland.
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In early 2000, Chameleon Systems Incorporated and Memorial University formed a research agreement to evaluate the viability of the Chameleon Systems CS2112 Reconfigurable Communications Processor (RCP) for use in implementing popular cryptographic algorithms. The CS2112 has a coarse grain reconfigurable architecture, capable of run time reconfigurability. -- The benefit of coarse grain reconfigurable architectures is that they can offer many of the flexibilities found in software, such as reprogrammability and ease of modification to implementation, while giving performance advantages of speed and hardware encapsulation. -- This research involves examining the implementation characteristics of two popular symmetric key block ciphers, RC5 and RC6, and two popular cryptographic hash algorithms, MD5 and SHA-1 with respect to the CS2112. -- RC5 was designed as an iterative loop and then expanded to provide a parallel pipeline to maximize the usage of the reconfigurable fabric. RC6 was designed as an iterative loop and a pipeline. For both hash algorithms, initial designs were drafted and performance figures were estimated from experience gained through simulation and testing on a CS2112 development board. -- By implementing these algorithms, the architecture of the CS2112 was evaluated for its suitability for cryptographic applications. Moreover, the reconfigurable fabric of the CS2112 was evaluated with respect to its support for the primitive operations that are required for cryptographic algorithms. -- The conclusions of this research and recommendations for future research are directly related to resource use on the CS2112. In particular, support for control and datapath logic, memory space, and global communication resources within the CS2112 were all design constraints. More specifically, it would be advantageous to have direct support for accessing memory without using datapath resources. Also hardware support for data dependent logical rotations and unsigned integer multiplications would greatly save resource usage and increase performance. Finally the design process for the CS2112 was sometimes time intensive and cumbersome, especially with respect to layout and placement of reconfigurable logic. Advances in the area of automatic placement and layout for coarse grain primitives would benefit the design process for the CS2112 greatly.
|Item Type:||Thesis (Masters)|
|Additional Information:||Bibliography: leaves 105-109.|
|Department(s):||Engineering and Applied Science, Faculty of|
|Library of Congress Subject Heading:||Adaptive computing systems; Data encryption (Computer science)|
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